1. Field of the Invention
The present invention relates to a semiconductor wafer, and more specifically, to a scribe line structure for wafer dicing and a method of making the same, to avoid interlayer delamination or peeling caused by a sawing process on a low-k/Cu wafer.
2. Description of the Prior Art
With the continued development of semiconductor process technology, and the miniaturization of the integrated circuit chip, many unneeded parasite capacitors are often formed in the inter-metal-dielectric (IMD) layer. Therefore, copper with lower resistance is gradually used in place of aluminum with higher resistance to be the material of the IMD layer, and the low dielectric constant (low-k) materials are gradually used in place of the silicon oxide dielectric materials, such as fluorinated silicate glass (FSG), phosphosilicate glass (PSG), or undoped silicate glass (USG), in order to decrease the resistances of conducting wires for the IMD layer or the dielectric constant of the dielectric layers, so as to mitigate the resistor-capacitor time delay effect.
After the integrated circuits of the semiconductor wafers are manufactured, dicing is the first step in the packaging process. The dicing quality can have a significant impact on yields as well as on device reliability. Dicing wafer with a grinding wheel is a typical method for many IC assembly plants. During the process of dicing, the grinding wheel or the cutter exerts a downward force upon the surface of the wafer. Crack (chipping) is unable to be avoided for the mechanical sawing. Especially, interconnect structures in IC areas have a higher metal density in the upper portion than in the lower portion, and accordingly peeling and interlayer delamination after wafer dicing are often found, which are more serious when the wafer is a low-k/Cu wafer. The term “metal density ” used herein relates to an amount of metal distributed in a certain area. This is a result of the properties of the copper and the low-k materials. The copper is fairly hard, and is more difficult to be cut in comparison with other materials in wafers. On the other hand, the low-k materials are soft or are porous structures, and the adhesion between the low-k materials and the other materials is rather poor. As the technology progresses and the scribe line for wafer dicing goes smaller, it is easy for this crack to penetrate active circuits and become a latent reliability problem of the final products.
Some conventional technologies have been used to improve the dicing quality. For example, FIG. 1 schematically shows a cross sectional view of a conventional scribe line structure 1 including a plurality of metal layers 11, also referred to as the scribe area interconnect layers, disposed in a dielectric layer 20 on a substrate 10. The metal layers 11 each have slots 12 uniformly distributed therein with a same pitch distance. The top metal layer 13 is a wholly metal pad. Not all the metal layers are shown, and metal vias (if exist) are skipped over for simplification and easy reading. FIG. 2 schematically shows a cross sectional view of a conventional scribe line structure 2 including a plurality of metal layers 21 and the top metal layer 23 disposed in the dielectric layer 20 on the substrate 10, each having slots 22 uniformly distributed therein. However, both scribe line structures 1 and 2 still cannot avoid a worse dicing result and reliability.
In other examples, FIG. 3 schematically shows a cross sectional view of a conventional scribe line structure 3 including a plurality of sets of metal vias 31 in the dielectric layer 20 on the substrate 10. There maybe or maybe not metal layers 32 disposed therein. The metal vias 31 are uniformly distributed with a same pitch distance. Not all the metal vias and the metal layers are shown for simplification and easy reading. FIG. 4 schematically shows a cross sectional view of a conventional scribe line structure 4 including a plurality of sets of metal vias 41 in the dielectric layer 20 on the substrate 10. There maybe or maybe not metal layers 42 disposed therein. Each set of the metal vias 41 has metal uniformly distributed in its own layer. The metal vias 41 are less dense to be disposed in the scribe line structure 4 than the metal vias 31 to be disposed in the scribe line structure 3. However, both scribe line structures 3 and 4 still cannot avoid a worse dicing result and reliability.
In a further example, a method for forming a semiconductor wafer to prevent the peeling and the interlayer delamination of material layers is disclosed in U.S. patent application Ser. No. 11/611,888 (assigned to the same assignee of the present application), in which a metal layer is formed in the low-k dielectric layer in the scribe line area and the metal layer comprises at least a slot parallel to the scribe line area, as shown in FIG. 5, a schematic top view of the metal layer 15 with slots 17 parallel to a dicing direction 9. The slots 17 are uniformly distributed in the metal layer 15.
As to improve reliability of ICs, a novel scribe line structure for wafer dicing and a method of making the same to avoid the interlayer delamination or peeling problem is till needed.